The inventive concept relates generally to memory controllers, memory systems including same, and/or methods of operating a memory controller or memory system. More specifically, the inventive concept relates to memory controllers, flash memory based memory systems and methods of operating same.
Certain contemporary electronic devices incorporate memory resources that may include a ‘built-in flash memory’ or a ‘system on chip’ (SoC) device. That is, one or more flash memory cell array(s) and related peripheral circuits may be disposed on a single semiconductor chip to form, wholly or in part, an integrated circuit. The peripheral circuits may variously include a high voltage circuit, a logic circuit for a constituent microcontroller or processor, etc.
In a broad class of devices referred to hereafter as SoC memory systems, there are tradeoffs that usually must be made between size, power consumption, operating speed (or frequency) and data throughput (bandwidth). Generally speaking, greater bandwidth comes at higher unit cost and increased physical size (i.e., reduced component integration density). Accordingly, SoC memory systems will often include memory sub-systems or components providing high bandwidth capabilities (hereafter, “high bandwidth memory”) and others providing relatively lower bandwidth capabilities (“low bandwidth memory”). These different SoC memory subsystems or components are operationally distinct, at least in terms of performance, but are often configured in a multi-level scheme to address disparate needs and tradeoffs presented by operation of the constituent SoC memory system.
In this context, a high bandwidth memory will exhibit relatively low data/signal latencies with respect to a central processing unit (CPU). The high bandwidth memory may also be directly accessed by the CPU via a dedicated interface. From a system configuration standpoint, therefore, the high bandwidth memory may be considered a low-level memory. In contrast, a low bandwidth memory is configured to access other SoC memory system components using a system bus protocol. As such the low bandwidth memory may be considered a high-level memory.
Contemporary SoC memory systems demand large data storage capacity, and therefore usually include large capacity data storage devices.
Given these common aspects of a SoC memory system, various operating methods have been proposed to efficiently store and access data. One conventionally understood method in this regard in the so-called ‘bank memory extension method’. The bank memory expansion method is a method of mapping interchangeable physical memories to a same address space in order to increase the amount of usable memory. However, when the bank memory extension method is used to control operation of contemporary SoC memory systems certain latency (or delay) problem may adversely effect overall performance. That is, accessing a low bandwidth memory in a Soc memory system using a system bus protocol may introduce added signal delay, thereby degrading performance. For example, in the foregoing configuration it is often necessary to frequently change (or update) an extended address associated with the bank extension of the memory.